Perspectives for the Use of Field Programmable Gate Arrays for Finite Element Computations

We have studied how the solution of partial differential equations by means of finite element methods could be accelerated using Field Programmable Gate Arrays (FPGAs). First, we discuss in general the capabilities of current FPGA technology for floating-point implementations of number crunching. Based on practical results for basic floating-point operators performance limits are outlined. Then the perspectives for the implementation of LU decomposition with a state-of-the-art FPGA chip are addressed. It is estimated that, compared with a modern CPU, a speedup by a factor of 10-20 can be expected using a single off-the-shelf FPGA.